The invention relates to integrated circuits, and more particularly, to memory systems and storing and accessing data.
Many electronic systems include memory to store information. A wide variety of memories are available from many suppliers, and new vendors and types of memory become available frequently. For flexibility purposes, electronic systems commonly accommodate several types of memory, for example by checking the memory to identify its operating parameters and other characteristics. The electronic system may then configure its resources accordingly.
One technique for accommodating different types of memory identifies memory chips with parallel presence detect (PPD) techniques. PPD uses a separate pin for each bit of information, which means that only the speed and density of the memory module are ordinarily provided because of the limited space for pins.
An alternative technique uses serial presence detect (SPD). SPD information is stored in an electrically erasable programmable read-only memory (EEPROM) chip on a memory module that provides supplemental information relating to the memory. Typically, SPD information comprises basic input/output system (BIOS) information, such as the module""s type, size, data width, speed, and voltage characteristics. The BIOS uses this information to configure the memory and/or other system resources properly for reliability and performance.
In many systems, the EEPROM on an SPD memory module is accessed for the SPD information during system boot-up via a system management bus (SMBus). Referring to FIG. 6, a processor 602 accesses the SMBus 610 by transmitting signals via a north bridge circuit 602 and a PCI bus 604 to a south bridge circuit 614. The south bridge circuit 614 provides the interface with the SMBus 610, as well as for other low-speed and or low bandwidth devices. The SMBus 610 interfaces with the memory module 612 through multiple pins, such as a serial clock for presence-detect (SCL) pin and a serial presence-detect data (SDA) pin, together with three device address (SA(2:0)) pins.
The addition of pins to accommodate the SMBus for SPD access, however, affects the cost and function of the memory module 612. As the number of pins increases, so does the cost of the memory module 612, especially for high pin-count systems, such as those including 200 to 300 or more pins. Further, each pin occupied by an SPD function displaces other functionality that could be assigned to that pin.
An electronic system according to various aspects of the present invention is configured to access a memory module that may operate in multiple modes. The memory module includes at least one connection configured to perform different functions when the memory module is operating in the different modes. In one embodiment, the memory operates in a normal mode and an SPD mode. While in SPD mode, the connection performs one or more SPD functions, such as operating as an interface connection to provide SPD information. In normal mode, however, the connection serves a function associated with normal operation of the module, such as addressing functions.